mindspeed technologies? offers its first 4-port ds3/e3/sts-1 jitter-attenuator and desynchronizer based on djat technology mindspeeds djat technology performs critical jitter- attenuation and signal desynchronization functions to improve performance and reliability in both telecommun- ciations and data communications equipment surrounding the edge of the optical network. this high density, low power solution is designed for transmission applications including add/drop multiplexers, routers, atm multi-service switches, digital cross connects, and ds3 to sts-1 mappers. the m28324 4-port djat device can be combined with line interface units (lius) and mapper devices in addressing traffic-aggregation equipment needs in converting high-speed synchronous transport signal-1 (sts-1) streams to asynchronous lower-speed ds3/e3 data rates for systems used in data centers and points of presence (pops). the 4-port m28324 djat leverages mindspeeds advance digital signal processing techniques along, with extensive knowledge of analog mixed signal design, that provide the first solution of its kind to adapt and fully smooth a sts-1 clock (with overhead gaps) to a network compliant ds3 or e3 line clock. the m28324 4-port djat complies with telcordia gr-253 and gr-499, etsi tbr-24, ansi t1.105.03b, as well as itu g.751, g.755, g.783, and g.823 standards. for category i interfaces, the m28320 12-port djat device smooths the inherent jitter due to demapping, bit stuffing and pointer adjustments in ds3 or e3 payloads extracted from sts-1 frames, generating a network compliant clock. the m28324 4-port djat seamlessly interfaces with mindspeeds ds3/e3/sts-1 liu devices m28331/2/3 (1/2/3-port), m28335 (12-port), and cx28365 (12-port ds3/e3 framer with atm tc) providing a complete solution for high density ds3/e3 line cards. jitter definition jitter is defined as the short-term variations of the significant instants of any signal from their ideal position in time. the short-term variations are phase oscillations of the digital signal. clock jitter can lead to incorrect data bit sampling, resulting in bit errors. jitter can be caused by any or all of the following: C interference C stuffing jitter C oscillator phase noise C demapping jitter C signal distortion C pointer jitter > high density: up to 4 inde- pendent jitter-attenuators and desynchronizers for ds3/e3, and sts-1 in one package > low power: <185 mw maximum power consumption > programmable fifo depth optimal for sonet/sdh > crystal-less jitter-attenuation > programmable clocking of both inputs and outputs on either edge > two prbs generator/detector per channel > one second timer for event latching > ability to dejitter ami or nrz input data > ability to independently bypass the jat for each channel > power-down control for each channel > small 15 mm bga package > single 3.3 v supply > > key features highly-integrated, fully-featured 4-port ds3/e3/sts-1 jitter-attenuator and sts-1 to ds3/e3 desynchronizer m28324 digital jitter-attenuator (djat)
jitter-attenuator and desynchronizer jitter-attenuator (jat) smooths the phase differences of clock signals due to phase variations between stratum clocks, bit stuffing, pointer adjustments due to frequency differences, and demapping of sts-1 payloads. there are two modes of operation for the m28324 4-port djat. the first involves attenuating jitter from a clock signal of e3, ds3, or sts-1 data rates. this is typically referred to as a category ii interface. clock jitter on this interface is also referred to as line timing jitter. the second mode of opera- tion, for a category i interface, involves extracting an e3 or ds3 payload from a sts-1 frame. clock jitter on this interface is also referred to as demapping jitter. microprocessor interface in hardware mode, the m28324 4-port device requires little or no control and may be statically configured. the m28324 4-port device also supports a 4 signal serial and a parallel 8-bit micro- processor interface that allows access to extended features such as the prbs generators and bit error rate (ber) counters. control and status registers are memory mapped. www.mindspeed.com/salesoffices general information: (949) 579-3000 headquarters C newport beach 4000 macarthur blvd., east tower newport beach, ca 92660-3007 order# 500295a m01-0637 ? 2002 mindspeed technologies ? , a conexant business. all rights reserved. mindspeed and the mindspeed logo are trademarks ofmindspeed technologies. all other trademarks are the property oftheir respective owners. although mindspeed technologies strives for accuracy in all its publications, this material may contain errors or omissions and is subject to change without notice. this material is provided as is and without any express or implied warranties, including merchantability, fitness for a particular purpose and non-infringement. mindspeed technologies shall not be liable for any special, indirect, incidental or consequential damages as a result of its use. ? high density: up to 4 independent jitter-attenuators and desynchro- nizers for ds3/e3,and sts-1 in one package ? low power: <185 mw maximum power consumption ? programmable fifo depth optimal for sonet/sdh ? crystal-less jitter-attenuation ? programmable clocking of both inputs and outputs on either edge ? two prbs generator/detector per channel ? one second timer for event latching ? ability to dejitter ami or nrz input data ? ability to independently bypass the jat for each channel ? power-down control for each channel ? small 15 mm bga package ? single 3.3 v supply applications ? digital cross-connect systems ? multi-service atm switches ? routers ? add/drop multiplexers product features m28324 prbs (gen/det) jat 3 jat 0 control prbs (gen/det) timing control & pll fifo & phase detector din_p(0) din_n(0) wclk (0) refclk(0) reset int mode0 e3 jat_en(3:0) pd(3:0) mode1 sclk sdin sdout cs oe wr addr(aa,8:0) data(7:0) scclk in_smp out_smp jat_mode pad_oe ds3mode dout_p(0) dout_n(0) rclk (0) functional block diagram
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